AD4056BCPZ-R2 datasheet(35/67 Pages) AD

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Data Sheet

AD4050/AD4056

MODES OF OPERATION

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Rev. A | 35 of 67

CHOP TIMING DIAGRAMS

Figure 55. Sample Mode Timing with CHOP Enabled

Figure 56. Averaging Mode Timing with CHOP Enabled

Figure 57. Burst Averaging Mode Timing with CHOP Enabled

AUTONOMOUS MODES

The autonomous modes allow the AD4050/AD4056 to autonomous-

ly monitor the input signal to detect out-of-range events. The auton-

omous modes feature lower power dissipation than nonautonomous

modes, because the ADC core enters a low-power comparator

mode, as described in the Comparator Operation section (see Table

1 for power dissipation specifications for each mode).

The AD4050/AD4056 offer two autonomous modes, monitor mode

and trigger mode. Both autonomous modes are described in the

subsequent sections. When either autonomous mode is selected,

the ADC core functions as a window comparator, and the ADC

sampling clock is driven by the internal timer, as described in the

Comparator Operation section. The sampling clock frequency is set

by the FS_BURST_AUTO bit field in the TIMER_CONFIG register

(see Table 44).

The comparator performs the following four sample-and-compari-

son operations in a repeated sequence, each taking one sample

period to execute, for a total sequence time of four sample periods:

1. VIN ≥ MAX_LIMIT

2. VIN ≤ MAX_LIMIT − MAX_HYST

3. VIN ≥ MIN_LIMIT + MIN_HYST

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