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AX88172ATF bảng dữ liệu(PDF) 34 Page - ASIX Electronics Corporation |
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AX88172ATF bảng dữ liệu(HTML) 34 Page - ASIX Electronics Corporation |
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34 / 45 page ![]() ASIX ELECTRONICS CORPORATION 34 AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 9.4.8 I2C Interface Timing I2C Master Controller Timing table: Symbol Parameter Standard mode (Typ) Fast mode (Typ) Unit Fclk I2C_SCL clock frequency. 100 400 KHz Thigh High period of the I2C_SCL clock. 4.0 1.0 µs Tlow Low period of the I2C_SCL clock. 6.0 1.5 µs Tsu_sta Setup time for a repeated START (Sr) condition. 4.0 1.0 µs Thd_sta Hold time of (repeated) START (S) condition. After this period, the first clock pulse is generated 4.0 1.0 µs Tsu_dat Data Setup time. 2.0 0.5 µs Thd_dat Data Hold time. 4.0 1.0 µs Tsu_sto Data Setup time for STOP (P) condition. 4.0 1.0 µs Tbuf Bus free time between a STOP and START condition. Note 1 Note 1: It will be much greater than 22us because several factors can influence this parameter such as USB system utilization, the CBW structure, and High/Full speed, etc. I2C Slave Controller Timing Table: Symbol Parameter Min Typ Max Unit Fclk I2C_SCL clock frequency. - - 390 KHz High period of the I2C_SCL clock in Fast mode. 0.6 - - µs Thigh High period of the I2C_SCL clock in Standard mode. 4.0 - - µs Tlow Low period of the I2C_SCL clock. 0.4 - - µs Tsu_sta Setup time for a repeated START (Sr) condition. 1 - - Tsys_clk (Note 2) Thd_sta Hold time of (repeated) START (S) condition. After this period, the first clock pulse is generated 3 - - Tsys_clk Tsu_dat Data Setup time. 3 - - Tsys_clk Thd_dat Data Hold time. 0.4 - - µs Tsu_sto Data Setup time for STOP (P) condition. 1 - - Tsys_clk Tbuf Bus free time between a STOP and START condition. - - - Note 2: Tsys_clk =33.33ns for 30MHz operating system clock. |
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