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Bosch Sensortec | BMP280 Data sheet

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Modifications reserved | Data subject to change without notice

Document number: BST-BMP280-DS001-26 Revision_1.26_102021

Table 27: I²C timings

Parameter

Symbol

Condition

Min

Typ

Max

Units

SDI setup time

tSU;DAT

S&F Mode

HS mode

160

SDI hold time

tHD;DAT

S&F Mode, Cb≤100 pF

S&F Mode, Cb≤400 pF

HS mode, Cb≤100 pF

HS mode, Cb≤400 pF

115

150

SCK low pulse

tLOW

HS mode, Cb≤100 pF

VDDIO = 1.62 V

160

SCK low pulse

tLOW

HS mode, Cb≤100 pF

VDDIO = 1.2 V

210

The above-mentioned I2C specific timings correspond to the following internal added delays:

•

Input delay between SDI and SCK inputs: SDI is more delayed than SCK by typically

100 ns in Standard and Fast Modes and by typically 20 ns in High Speed Mode.

•

Output delay from SCK falling edge to SDI output propagation is typically 140 ns in

Standard and Fast Modes and typically 70 ns in High Speed Mode.

5.4.3

SPI timings

The SPI timing diagram is in Figure 13, while the corresponding values are given in

Table 28

. All timings apply both to 4- and 3-wire SPI.

CSB

SCK

T_setup_csb

T_low_sck

T_high_sck

T_hold_csb

SDI

T_setup_sdi

T_hold_sdi

SDO

T_delay_sdo

Figure 13: SPI timing diagram

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