ADBMS6821 datasheet(17/28 Pages) AD

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Data Sheet

ADBMS6821/ADBMS6822

THEORY OF OPERATION

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Rev. B | 17 of 28

Figure 34. isoSPI Differential Pulse Detail

ISOSPI PULSE SPECIFICATIONS

Figure 34 shows the timing specifications for the +1 and −1 isoSPI

pulses. The same timing specifications apply to either version of

these symmetric pulses. In the isoSPI Pulse Timing Specifications

section, these specifications are further separated into CS (long)

and data (short) parameters.

A valid pulse must meet the minimum specification for t1/2PW and

the maximum specification for tINV. In other words, the half-pulse

width must be long enough to pass through the appropriate pulse

timer, but short enough for the inversion to begin within the valid

window of time. The response observed at PICO, POCI, or CS

occurs after the tDEL delay from the pulse inversion.

ISOSPI INTERACTION AND TIMING

The timing diagrams in Figure 35 and Figure 36 show how an

isoSPI in controller mode (connected to a SPI controller) interacts

with an isoSPI in peripheral mode (connected to a SPI peripheral).

Figure 35 shows the operation with PHA = 0 (and shows SCK

signals for POL = 0 or 1). Figure 36 shows the timing diagram for

PHA = 1. Although not shown, it is acceptable to use different SPI

modes (PHA and POL settings) on the controller and peripheral

devices.

A controller SPI device initiates communication by lowering CS.

The ADBMS6821/ADBMS6822 transceivers convert this transition

into a long −1 pulse on the IP and IM pins. The pulse traverses the

isolation barrier (with an associated cable delay) and arrives at the

IP and IM pins of the peripheral transceiver. When validated, the

long −1 pulse is converted back into a falling CS transition, this time

supplied to the peripheral SPI device. If peripheral PHA = 1, SCK

also leaves the idle state at this time.

Before the controller SPI device supplies the first latching clock

edge (usually a rising edge, but for exceptions, see Table 20), the

peripheral transceiver must transmit the initial peripheral data bit,

SN. The value of the SN is determined by sampling the state of

POCI.

If POCI = 0, the peripheral transmits a short −1 pulse to the control-

ler. The controller transceiver receives and decodes the pulse and

sets the controller POCI = 0 (matching the peripheral). However, if

the peripheral POCI = 1, the peripheral does not transmit a pulse.

The controller interprets this null response as a 1 and sets the

controller POCI = 1. This behavior makes it possible to connect

multiple peripheral transceiver devices to a single cable with no

conflicting signals (for more information, see the Multidrop section).

After the falling CS sequence, every latching clock edge on the

controller converts the state of the PICO pin into an isoSPI data

pulse (MN, MN − 1, … M0) while simultaneously latching the data

bit of the peripheral. As the peripheral transceiver receives each

data bit, it sets the peripheral PICO pin to the proper state and

then generates an SCK pulse before returning the POCI data of the

peripheral (either as a short −1 pulse, or as a null).

At the end of communication, the final data bit sent by the periph-

eral (either as a pulse or null) is ignored by the controller. The

peripheral transceiver must return a data bit because it cannot

predict when communications cease. The controller SPI device can

then raise CS, which is transmitted to the peripheral in the form of

a long +1 pulse. The process ends with the peripheral transceiver

transitioning CS high and returning SCK to the idle state (if PHA =

1).

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