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CORTEX-R82 bảng dữ liệu(PDF) 12 Page - Arm Limited (or its affiliates).

tên linh kiện CORTEX-R82
Giải thích chi tiết về linh kiện  Arm Cortex-R82 Processor Datasheet
PDF  13 Pages
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nhà sản xuất  ARM [Arm Limited (or its affiliates).]
Trang chủ  https://www.arm.com/
Logo ARM - Arm Limited (or its affiliates).

CORTEX-R82 bảng dữ liệu(HTML) 12 Page - Arm Limited (or its affiliates).

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12
Cortex-R82 Configuration Options
Feature
Options
Cache protection
No RAM protection included.
RAM protection included.
ELA
No ELA included.
ELA included.
L2 cache size
No L2 cache.
L2 cache present with size of 128KB, 192KB, 256KB,
384KB, 512KB, 768KB, 1024KB, 1536KB, 2048KB,
3072KB, or 4096KB.
L2 cache data RAM input latency
1-cycle latency.
2-cycle latency.
2-cycle latency with an extra hold cycle.
L2 cache data RAM output latency
2-cycle latency.
3-cycle latency.
L2 cache data RAM output register slice
No register slice.
Register slice included.
L2 cache data RAMs clock pulse stretch
Stretched.
Not stretched.
Power on reset state for the Power Policy Units (PPUs)
Cluster and all core PPUs reset to off.
Cluster and core 0 PPUs reset to on. Any other
core PPUs reset to off.
Cluster and all core PPUs reset to on.
Number of EL2 Memory Protection Unit (MPU) regions
0, 16, or 32
Number of EL1 MPU regions
0, 16, or 32
Main master bus type
Main master is AXI-5.
Main master is CHI.
VMSA support
EL1-MMU included.
EL1-MMU not included.
Advanced SIMD and floating-point support
No Advanced SIMD and no floating-point
support included.
Advanced SIMD and half precision, single
precision, and double precision floating-point
functionality included.
Number of wait states incurred by
accesses to the ITCM
0, 1, 2, 3
ITCM clock pulse stretch
Stretched.
Not stretched.
Data Tightly Coupled Memory (DTCM) size
0 (DTCM logic is always present but the size can be 0),
16KB, 32KB, 64KB, 128KB, 256KB, 512KB, 1024KB.
Instruction Tightly Coupled Memory (ITCM) size
0 (ITCM logic is always present but the size can be 0),
16KB, 32KB, 64KB, 128KB, 256KB, 512KB, 1024KB.
Number of wait states that are incurred by
accesses to the DTCM
0,1, 2, 3
DTCM clock pulse stretch
Stretched.
Not stretched.
Supporting technical documents coming soon.
Learn more about the processor here.



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