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Arm Cortex-M4 Datasheet

Datasheet

Overview

The Cortex-M4 processor is developed to address digital signal control markets that demand

an efficient, easy-to-use blend of control and signal processing capabilities. The combination

of high-efficiency signal processing functionality with the low-power, low-cost and ease-of-

use benefits of the Cortex-M family of processors satisfies many markets. These industries

include motor control, automotive, power management, embedded audio and industrial

automation markets.

Features

Feature

Description

Architecture

Armv7E-M

Bus Interface

3x AMBA AHB-Lite interface (Harvard bus architecture)

AMBA ATB interface for CoreSight debug components

ISA Support

Thumb/Thumb-2

Pipeline

3-stage + branch speculation

DSP Extension

Single-cycle 16/32-bit MAC

Single-cycle dual 16-bit MAC

8/16-bit SIMD arithmetic

Hardware Divide (2-12 cycles)

Floating-Point Unit

Optional single precision floating point unit (FPU)

IEEE 754 compliant

Memory Protection

Optional 8-region MPU with sub regions

and background region

Bit Manipulation

Integrated Bit Field Processing Instructions

& Bus Level Bit Banding

Interrupts

Non-maskable interrupt (NMI) + 1 to 240 physical interrupts

Interrupt Priority Levels

8 to 256 priority levels

Wake-up Interrupt

Controller

Optional

Sleep Modes

Integrated WFI and WFE Instructions and Sleep On Exit capability

Sleep & Deep Sleep Signals

Optional Retention Mode with Arm Power Management Kit

Debug

Optional JTAG and Serial Wire Debug ports

Up to 8 Breakpoints and 4 Watchpoints

Trace

Optional Instruction Trace (ETM), Data Trace (DWT),

and Instrumentation Trace (ITM)

Figure 1: Block diagram

of the Cortex-M4 processor