2

Processor features

The Armv6-M Thumb® instruction set with Thumb-2 technology

Optionally, an Armv6-M compliant 24-bit SysTick timer

A 32-bit hardware multiplier. This can be the standard single-cycle

multiplier, or a 32-cycle multiplier that has a lower area and

performance implementation

Support for either little-endian or byte invariant big-endian data accesses

The ability to have deterministic, fixed-latency, interrupt handling

Load/store-multiples and multicycle-multiplies that can be abandoned

and restarted to facilitate rapid interrupt handling

Armv6-M C Application Binary Interface (C-ABI) compliant exception model

enabling the use of pure C functions as interrupt handlers

Low power sleep-mode entry using WFI and WFE instructions, or the return

from interrupt sleep-on-exit feature

Block Diagram

Figure 2: Cortex-M0

processor components