ADP151WAUJZ-1.8-R7 datasheet(14/23 Pages) AD

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Data Sheet

ADP151

APPLICATIONS INFORMATION

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Rev. J | 14 of 23

less than 1% error. Capacitor C3 is necessary to stabilize the LDO.

A value of 1 µF is adequate.

Figure 34 through Figure 38 show the typical performance of the

4 V LDO circuit.

The noise performance of the 4 V LDO circuit is only about 1 µV

worse than the same LDO used at 3.3 V because the output noise

of the circuit is almost solely determined by the LDO and not the

external components. The small difference may be attributed to the

internally generated noise in the LDO ground current working with

R2. By keeping R2 small, this noise contribution can be minimized.

The PSRR of the 4 V circuit is as much as 10 dB poorer than the

3.3 V LDO with 500 mV of headroom because the ground current of

the LDO varies slightly with input voltage. This, in turn, modulates

VOFFSET and reduces the PSRR of the regulator. By increasing the

headroom to 1 V, the PSRR performance is nearly restored to the

performance of the fixed output LDO.

Figure 34. 4 V LDO Circuit, Typical Load Regulation over Temperature

Figure 35. 4 V LDO Circuit, Typical Line Regulation over Load Current

Figure 36. 4 V LDO Circuit, Typical RMS Output Noise, 10 Hz to 100 kHz

Figure 37. 4 V LDO Circuit, Typical PSRR vs. Load Current, 1 V Headroom

Figure 38. 4 V LDO Circuit, Typical PSRR vs. Load Current, 500 mV

Headroom

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