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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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MAS9090BS bảng dữ liệu(PDF) 5 Page - Micronas |
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MAS9090BS bảng dữ liệu(HTML) 5 Page - Micronas |
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5 / 30 page  DA9090B.001 January 14, 1998 5 TIMING SPECIFICATIONS x Master Clock Timing Parameter Symbol Conditions Min Typ Max Unit Frequency of MCLK fMCLK programmable 512 1536 2048 kHz Period of MCLK high/low fMCK = 512 tWHM tWLM Measured from VIH to VIH 878 1074 ns Period of MCLK high fMCK = 1536, 2048 tWHM Measured from VIH to VIH 80 ns Period of MCLK low fMCK = 1536, 2048 tWLM Measured from VIL to VIL 80 ns Rise time of MCLK tRM Measured from VIL to VIH 30 ns Fall time of MCLK tFM Measured from VIH to VIL 30 ns x PCM Interface Timing Parameter Symbol Conditions Min Typ Max Unit Hold time, MCLK low to FS low tHMLF 17 ns Setup time, FS high to MCLK low tSFML 30 ns Delay time, MCLK high to valid TX data tDMHT Load = 100pF 100 ns Delay time, MCLK low to TX disabled tDMLZ 10 100 ns Delay time, FS high to valid TX data tDFT Load = 100pF non-delayed mode only 100 ns Setup time, RX data valid to MCLK low tSRML 20 ns Hold time, MCLK low to invalid RX data tHMLR 10 ns Hold time, MCLK high to FS low tHMHF 30 ns Setup time, FS high to MCLK high tSFMH 30 ns Delay time, MCLK low to valid TX data tDMLT Load = 100pF 100 ns Delay time, MCLK high to TX disabled tDMHZ 10 100 ns Hold time, MCLK high to invalid RX data tHMHR 20 ns x Non-Delayed Data Timing Diagram 1 2 3 45 67 8/16 12 3 4 5 6 7 8/16 12 3 4 5 6 7 8/16 t SRML t HMLR t WHM t WLM t DMLZ t RM t FM t HMLF t SFML t DFT t DMHT MCLK FS TX RX In companded mode the timing is applied to 8 bits instead of 16 bits. |
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