MAS9090B datasheet(26/30 Pages) MICRONAS

26 / 30 page

DA9090B.001

January 14, 1998

Control Registers CR8 and CR9

The frequency of both frequency generators is

programmed by CR8 and CR9.

When

standard

frequency

range

selected

(CR10: DFT=0, HFT=0) the frequency is defined by

formulas: f1 = CR8 / 0.128 Hz and f2 = CR9 / 0.128

Hz, where CR8 and CR9 are decimal equivalents of

the register content. Thus any frequency between

7.8 Hz and 1992 Hz in 7.8 Hz step can be selected.

When

halved

frequency

range

selected

(CR10:DFT=0, HFT=1) the frequency is defined by

formulas: f1 = CR8 / 0.256 Hz and f2 = CR9 / 0.256

Hz. Thus any frequency between 3.9 Hz and 996 Hz

in 3.9 Hz step can be selected.

When

doubled

frequency

range

selected

(CR10:DFT=1, HFT=0) the frequency is defined by

formulas: f1 = CR8 / 0.064 Hz and f2 = CR9 / 0.064

Hz. Thus any frequency between 15.6 Hz and

3984 Hz in 15.6 Hz step can be selected.

Control Register CR10

Writing bit POR (7) high puts the MAS9090 in

power-on-reset state and all data and control

registers are cleared (including the POR bit).

Logic low written to bit SCA (6) sets the chip to scan

mode. During scan CI is the input and TX is the

output. Used only for device testing.

High written to bit HPT (5) bypasses the highpass

part of the TX bandpass filter.

When Bit EXT (4) is set active the two bit output of

the ADC is disabled and data is fed from pins CR

and DR. Used only for device testing.

With bit L0 (3) it is possible to loop internally from

TX to RX. Bit L1 (2) permits looping from the

expander output to the compressor input.

Frequency Range Selection

Bits DFT (1) and HFT (0) define the frequency range

of the tone generator output. Three modes are

possible: halved, standard and doubled with output

frequencies from 3.9…996 Hz and 7.8…1992 Hz,

15.6…3984 Hz respectively.

Control Register CR11

When bit BE (7) is high it permits the connection of

f1 squarewave pulse width modulated (PWM) ring

signal to buzzer driver output pin BZ. Signal can be

amplitude modulated (AM) with squarewave signal

f2.

When bit BE is low (buzzer disabled) the state of the

output pin BZ is logical inversion of bit BI (6). This

works also in power-down state.

When buzzer output is enabled (BE = 1) bit BI (6)

controls the polarity of the duty cycle selection.

BI = 1 means the duty cycle is calculated from the

relative width of the logic one. When BI = 0 the duty

cycle is calculated from the relative width of the logic

zero.

Bits BZ5:BZ0 (5:0) define the duty cycle of the PWM

squarewave, according to the following formula: duty

cycle = CR11(5:0) x 0.78125 %, where CR11 (5:0) is

the decimal equivalent of binary value BZ5:BZ0.

Control Register CR14 (for testing)

Bits AM2:AM0 (7:5) control the analog multiplexer.

Different analog test signals can be fed to test pads.

Test pads are not wire bonded in production

packages.

Bits DM2:DM0 (4:2) control the digital multiplexer.

Different test signals can be fed to the TX output

pin.

Bit MUX (1) connects the test outputs to the TX

output pin. It is for device testing.

Bit EDX (0) enables the TX output continuously. No

pull-up resistor is needed when TX pin is the only

output for the reading device and EDX is written

High.

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