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USB3290 bảng dữ liệu(PDF) 34 Page - SMSC Corporation |
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USB3290 bảng dữ liệu(HTML) 34 Page - SMSC Corporation |
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34 / 46 page ![]() Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet Revision 1.5 (11-02-07) 34 SMSC USB3290 DATASHEET 8.9 HS Detection Handshake – HS Downstream Facing Port Upon entering the HS Detection process (T0) XCVRSELECT and TERMSELECT are in FS mode. The DP pull-up is asserted and the HS terminations are disabled. The SIE then sets OPMODE to Disable Bit Stuffing and NRZI encoding , XCVRSELECT to HS mode, and begins the transmission of all 0's data, which asserts a HS K (chirp) on the bus (T1). The device chirp must last at least 1.0ms, and must end no later than 7.0ms after HS Reset T0. At time T1 the device begins listening for a chirp sequence from the downstream facing port. If the downstream facing port is HS capable then it will begin generating an alternating sequence of Chirp K’s and Chirp J’s (T3) after the termination of the chirp from the device (T2). After the device sees the valid chirp sequence Chirp K-J-K-J-K-J (T6), it will enter HS mode by setting TERMSELECT to HS mode (T7). Figure 8.4 provides a state diagram for Chirp K-J-K-J-K-J validation. Prior to the end of reset (T9) the device port must terminate the sequence of Chirp K’s and Chirp J’s (T8) and assert SE0 (T8-T9). Note that the sequence of Chirp K’s and Chirp J’s constitutes bus activity. The Chirp K-J-K-J-K-J sequence occurs too slow to propagate through the serial data path, therefore LINESTATE signal transitions must be used by the SIE to step through the Chirp K-J-K-J-K-J state diagram, where "K State" is equivalent to LINESTATE = K State and "J State" is equivalent to LINESTATE = J State. The SIE must employ a counter (Chirp Count) to count the number of Chirp K and Chirp J states. Note that LINESTATE does not filter the bus signals so the requirement that a bus state must be "continuously asserted for 2.5µs" must be verified by the SIE sampling the LINESTATE signals. Figure 8.4 Chirp K-J-K-J-K-J Sequence Detection State Diagram Detect K? Start Chirp K-J-K-J-K-J detection INC Chirp Count K State !K Detect J? INC Chirp Count J State !J Chirp Count != 6 & !SE0 Chirp Count = 0 Chirp Count != 6 & !SE0 Chirp Valid Chirp Invalid SE0 Chirp Count |
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