TA84006F/FG

2006-3-6

16

Test Circuit 9: VCMP, VOL (CMP), ROH (CMP)

(1)

Where output phase 2 is High (10.92 V) and phase 1 is Low (

= 9.88 V), set SW1 = A and measure

V2

= VOL (CMP).

(2)

Where output phase 1 is High (10.92 V) and phase 2 is Low (9.88 V), set SW1 = B and confirm that

5 V

× 10 kΩ/(10 kΩ + 13 kΩ) < V2 < 5 V × 10 kΩ/(10 kΩ + 7 kΩ).

Test Circuit 10: VRF, VOH (ISD), VOL (ISD)

(1)

Where VISD

= 0.55 V, set SW2 = A and measure V3 = VOH (ISD).

(2)

Where VISD

= 0.45 V, set SW2 = B and measure V3 = VOL (ISD).

17

1

2

27

29

4

10

11

12

13

14

15

18

19

28

30

3

6

25

16

7

24

21

20

9

TA84006F/FG

V2

V

10 k

Ω

B

SW1

A

17

1

2

27

29

4

10

11

12

13

14

15

18

19

28

30

3

6

25

16

7

24

21

20

9

TA84006F/FG

V3

V

0.1 mA

B

SW2

A

0.1 mA