LTC2945

5

Rev. C

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Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into pins are positive. All voltages are referenced to

ground, unless otherwise noted.

Note 3: An internal shunt regulator limits the INTVCC pin to a minimum of

5.9V. Driving this pin to voltages beyond 5.9V may damage the part. This

pin can be safely tied to higher voltages through a resistor that limits the

current below 35mA.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

fCONV

Conversion Rate (Continuous Mode)

l

6

7.5

9

Hz

tCONV

Conversion Time (Snapshot Mode)

ΔSENSE

VIN, ADIN

l

l

60

30

66

33

72

36

ms

ms

RADIN

ADIN Pin Input Resistance

VDD = 48V, ADIN = 3V

l

3

10

MΩ

IADIN

ADIN Pin Input Current

VDD = 48V, ADIN = 3V

l

±1

µA

I2C INTERFACE (VDD = 48V)

VADR(H)

ADR0, ADR1 Input High Threshold

l

2.1

2.4

2.7

V

VADR(L)

ADR0, ADR1 Input Low Threshold

l

0.3

0.6

0.9

V

IADR(IN)

ADR0, ADR1 Input Current

ADR0, ADR1 = 0V, 3V

l

±13

µA

IADR(IN,Z)

Allowable Leakage When Open

l

±7

µA

VOD(OL)

SDAO, SDAO, ALERT Output Low Voltage

ISDAO, ISDAO, IALERT = 8mA

l

0.15

0.4

V

ISDA,SCL(IN)

SDAI, SDAO, SDAO, SCL Input Current

SDAI, SDAO, SDAO, SCL = 5V

l

0

±1

µA

VSDA,SCL(TH)

SDAI, SCL Input Threshold

l

1.5

1.9

2.2

V

VSDA,SCL(CL)

SDAI, SCL Clamp Voltage

ISDAI, ISCL = 3mA

l

5.9

6.4

6.9

V

IALERT(IN)

ALERT Input Current

ALERT = 5V

l

0

±1

µA

I2C INTERFACE TIMING

fSCL(MAX)

Maximum SCL Clock Frequency

400

kHz

tLOW

Minimum SCL Low Period

0.65

1.3

µs

tHIGH

Minimum SCL High Period

50

600

ns

tBUF(MIN)

Minimum Bus Free Time Between Stop/Start Condition

0.12

1.3

µs

tHD,STA(MIN)

Minimum Hold Time After (Repeated) Start Condition

140

600

ns

tSU,STA(MIN)

Minimum Repeated Start Condition Set-Up Time

30

600

ns

tSU,STO(MIN)

Minimum Stop Condition Set-Up Time

30

600

ns

tHD,DATI(MIN)

Minimum Data Hold Time Input

–100

0

ns

tHD,DATO(MIN) Minimum Data Hold Time Output

300

600

900

ns

tSU,DAT(MIN)

Minimum Data Set-Up Time

30

100

ns

tSP(MAX)

Maximum Suppressed Spike Pulse Width

50

110

250

ns

tRST

Stuck Bus Reset Time

SCL or SDAI Held Low

25

33

ms

CX

SCL, SDAI Input Capacitance (Note 5)

5

10

pF

ELECTRICAL CHARACTERISTICS The

l

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VDD is from 4V to 80V unless otherwise noted. (Note 2)

Note 4: Internal clamps limit the SCL and SDAI pins to a minimum of

5.9V. Driving these pins to voltages beyond the clamp may damage the

part. The pins can be safely tied to higher voltages through resistors that

limit the current below 5mA.

Note 5: Guaranteed by design and not subject to test.

Note 6:

TUE

=

ACTUAL CODE

−IDEAL CODE

(

)

4096

× 100%

where IDEAL CODE is derived from a straight line passing through Code 0

at 0V and Theoretical Code of 4096 at VFS.

Note 7: ΔSENSE is defined as VSENSE+ – VSENSE–