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MIC4607A-2 bảng dữ liệu(PDF) 21 Page - Microchip Technology |
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MIC4607A-2 bảng dữ liệu(HTML) 21 Page - Microchip Technology |
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21 / 41 page ![]() 2024 Microchip Technology Inc. and its subsidiaries DS-20006957A-page 21 MIC4607A 5.7.2 DLY A capacitor connected to the DLY pin determines the amount of time the gate drive outputs are latched off before they can be restarted. During normal operation, the DLY pin is held low by an internal MOSFET. After an overcurrent condition is detected, the MOSFET turns off and the external capacitor is charged up by an internal current source. The outputs remain latched off until the DLY pin voltage reaches the VDLY+ threshold (typically 1.5V). The delay time can be approximately calculated using Equation 5-1. EQUATION 5-1: 5.7.3 FLT/ This open-drain output is pulled low while the gate drive outputs are latched off after an over-current condition. It will de-assert once the DLY pin has reached the VDLY+ threshold and a rising edge occurs on any LI pin (for the MIC4607A-1) or a falling edge on any PWM pin (MIC4607A-2). During normal operation, the internal pull-down MOS- FET is of the pin is high impedance. A pull-up resistor must be connected to this pin. tDLY CDLY VDLY- IDLY ---------------------------------- = |
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