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TLV755P bảng dữ liệu(PDF) 3 Page - Texas Instruments |
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TLV755P bảng dữ liệu(HTML) 3 Page - Texas Instruments |
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3 / 49 page ![]() 4 Pin Configuration and Functions 1 OUT 2 GND 5 3 EN 4 IN Not to scale Figure 4-1. DQN Package, 4-Pin X2SON (Top View) 1 IN 2 GND 3 EN 4 NC 5 OUT Not to scale Figure 4-2. DBV Package, 5-Pin SOT-23 (Top View) OUT NC IN 1 2 3 4 5 Thermal Pad Not to scale GND EN Figure 4-3. DYD Package, 5-Pin SOT-23 With Exposed Thermal Pad (Top View) 1 OUT 6 IN 2 NC 5 NC 3 GND 4 EN Not to scale Thermal Pad NC = no internal connection. Figure 4-4. DRV Package, 6-Pin WSON With Exposed Thermal Pad (Top View) Table 4-1. Pin Functions PIN TYPE(2) DESCRIPTION NAME DQN DBV DYD DRV EN 3 3 3 4 I Enable pin. Drive EN greater than VHI to turn on the regulator. Drive EN less than VLO to place the low-dropout regulator (LDO) into shutdown mode. GND 2 2 2 3 — Ground pin. IN 4 1 1 6 I Input pin. A capacitor with a value of 1µF or larger is required from this pin to ground.(1) See the Input and Output Capacitor Selection section for more information. NC — 4 4 2, 5 — No internal connection. OUT 1 5 5 1 O Regulated output voltage pin. A capacitor with a value of 1µF or larger is required from this pin to ground.(1) See the Input and Output Capacitor Selection section for more information. Thermal pad Pad — Pad Pad — Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND. (1) Make sure the nominal input and output capacitance is greater than 0.47µF. Throughout this document the nominal derating on these capacitors is 50%. Make sure the effective capacitance at the pin is greater than 0.47µF. (2) I = Input; O = Output www.ti.com TLV755P SBVS320D – NOVEMBER 2017 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TLV755P |
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