TC74HC221AP/AF/AFN

2007-10-01

4

Timing Chart

Functional Description

(1)

Stand-by state

comparators that relate to the timing of the output pulse, and two reference voltage supplies turn off.

The total supply current is only leakage current.

(2)

Trigger operation

Trigger operation is effective in any of the following three cases. First the condition where the

A

input is low, and the B input has a rising signal; second, where the B input is high, and the A input

has a falling signal; and third, where the A input is low and the B input is high, and the CLR

input has a rising signal.

voltage level falls to the internal reference voltage Vref L, the output of C1 becomes low. The flip-flop

constant of external capacitor Cx and resistor Rx.

Upon the triggering, output Q becomes high, following some delay time of the internal F/F and

gates. It stays high even if the voltage of Rx/Cx changes from falling to rising. When Rx/Cx reaches

the internal reference voltage Vref H, the output of C2 becomes low, the output Q goes low and C2

stops its operation. That means, after triggering, when the voltage level of the Rx/Cx node reaches

Vref H, the IC returns to its MONOSTABLE state.

With large values of Cx and Rx, and ignoring the discharge time of the capacitor and internal

delays of the IC, the width of the output pulse, tw (OUT), is as follows:

tw (OUT)

= 1.0 Cx Rx

(3)

Reset operation

In normal operation, CLR input is held high. If CLR is low, a trigger has no effect because the Q

This means if CLR input is set low, the IC goes into a wait state.