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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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SN74LVC166APWR bảng dữ liệu(PDF) 6 Page - Texas Instruments |
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SN74LVC166APWR bảng dữ liệu(HTML) 6 Page - Texas Instruments |
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6 / 34 page  5.6 Timing Characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER DESCRIPTION CONDITION VCC -40°C to 125°C UNIT MIN MAX tW Pulse duration CLK 1.2 V ± 0.1 V 7 ns tSU Setup time SH/LD high before CLK↑ 1.2 V ± 0.1 V 16.5 ns tSU Setup time SER before CLK↑ 1.2 V ± 0.1 V 10.1 ns tSU Setup time CLK INH before CLK↑ 1.2 V ± 0.1 V 1 ns tSU Setup time Data before CLK↑ 1.2 V ± 0.1 V 10 ns tSU Setup time CLR inactive before CLK↑ 1.2 V ± 0.1 V 10.1 ns tH Hold time SER data after CLK↑ 1.2 V ± 0.1 V 0.4 ns tH Hold time Parallel data after SH/LD↓ 1.2 V ± 0.1 V 1.8 ns tH Hold time SH/LD high after CLK↑ 1.2 V ± 0.1 V 0 ns tH Hold time CLK INH high after CLK↑ 1.2 V ± 0.1 V 0.4 ns tH Hold time Data after CLK↑ 1.2 V ± 0.1 V 1 ns tW Pulse duration CLR low 1.5 V ± 0.15 V 6.9 ns tW Pulse duration SH/LD low 1.5 V ± 0.15 V 6.9 ns tW Pulse duration CLK 1.5 V ± 0.15 V 7 ns tSU Setup time SH/LD high before CLK↑ 1.5 V ± 0.15 V 10 ns tSU Setup time SER before CLK↑ 1.5 V ± 0.15 V 10.1 ns tSU Setup time CLK INH before CLK↑ 1.5 V ± 0.15 V 1 ns tSU Setup time Data before CLK↑ 1.5 V ± 0.15 V 10 ns tSU Setup time CLR inactive before CLK↑ 1.5 V ± 0.15 V 10.1 ns tH Hold time SER data after CLK↑ 1.5 V ± 0.15 V 1.2 ns tH Hold time Parallel data after SH/LD↓ 1.5 V ± 0.15 V 1.9 ns tH Hold time SH/LD high after CLK↑ 1.5 V ± 0.15 V 1 ns tH Hold time CLK INH high after CLK↑ 1.5 V ± 0.15 V 0.6 ns tH Hold time Data after CLK↑ 1.5 V ± 0.15 V 1.8 ns tW Pulse duration CLR low 1.8 V ± 0.15 V 6.9 ns tW Pulse duration SH/LD low 1.8 V ± 0.15 V 6.9 ns tW Pulse duration CLK 1.8 V ± 0.15 V 7 ns tSU Setup time SH/LD high before CLK↑ 1.8 V ± 0.15 V 8 ns tSU Setup time SER before CLK↑ 1.8 V ± 0.15 V 10.1 ns tSU Setup time CLK INH before CLK↑ 1.8 V ± 0.15 V 1 ns tSU Setup time Data before CLK↑ 1.8 V ± 0.15 V 8 ns tSU Setup time CLR inactive before CLK↑ 1.8 V ± 0.15 V 10.1 ns tH Hold time SER data after CLK↑ 1.8 V ± 0.15 V 0.2 ns tH Hold time Parallel data after SH/LD↓ 1.8 V ± 0.15 V 0.8 ns tH Hold time SH/LD high after CLK↑ 1.8 V ± 0.15 V 0 ns tH Hold time CLK INH high after CLK↑ 1.8 V ± 0.15 V 0.3 ns tH Hold time Data after CLK↑ 1.8 V ± 0.15 V 1 ns tW Pulse duration CLR low 2.5 V ± 0.2 V 5.4 ns tW Pulse duration SH/LD low 2.5 V ± 0.2 V 5.4 ns tW Pulse duration CLK 2.5 V ± 0.2 V 4.5 ns tSU Setup time SH/LD high before CLK↑ 2.5 V ± 0.2 V 4.5 ns tSU Setup time SER before CLK↑ 2.5 V ± 0.2 V 5.9 ns tSU Setup time CLK INH before CLK↑ 2.5 V ± 0.2 V 1 ns SN74LVC166A SCLSA15 – MAY 2024 www.ti.com 6 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: SN74LVC166A |
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