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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

Product data sheet

Rev. 03 — 12 November 2004

13 of 20

Philips Semiconductors

74HC75

Quad bistable transparant latch

VM = 0.5 × VI.

Fig 9.

Waveforms showing the latch enable input (LEnn) pulse width, the latch enable

input to outputs (nQ, nQ) propagation delays and the output transition times

Test data is given in Table 9.

Definitions for test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

Fig 10. Load circuitry for switching times

Table 9:

Test data

Supply

Input

Load

VCC

VI

tr, tf

CL

2.0 V

VCC

6 ns

50 pF

4.5 V

VCC

6 ns

50 pF

6.0 V

VCC

6 ns

50 pF

5.0 V

VCC

6 ns

15 pF

nD input

LEnn input

nQ output

nQ output

tW

VM

VM

VM

001aab857

tPHL

tPLH

tTHL

tTLH

tTHL

tPLH

tPHL

tTLH

mna101

VCC

VI

VO

RT

CL

PULSE

GENERATOR

D.U.T.

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