công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

STA538 bảng dữ liệu(PDF) 20 Page - STMicroelectronics

tên linh kiện STA538
Giải thích chi tiết về linh kiện  2 x 1.3 W class-D amplifier with analog or digital input 2.0 multichannel digital audio processor with FFX
PDF  59 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STA538 bảng dữ liệu(HTML) 20 Page - STMicroelectronics

Back Button STA538 Datasheet HTML 16Page - STMicroelectronics STA538 Datasheet HTML 17Page - STMicroelectronics STA538 Datasheet HTML 18Page - STMicroelectronics STA538 Datasheet HTML 19Page - STMicroelectronics STA538 Datasheet HTML 20Page - STMicroelectronics STA538 Datasheet HTML 21Page - STMicroelectronics STA538 Datasheet HTML 22Page - STMicroelectronics STA538 Datasheet HTML 23Page - STMicroelectronics STA538 Datasheet HTML 24Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 20 / 59 page
background image
PLL
STA538
20/59
PLL filter
Figure 5 shows the PLL filter scheme. Recommended values are R1 = 12.5 k
Ω,
C1 = 250 pF, and C2 = 82 pF.
Figure 5.
PLL filter scheme
Table 10 on page 14 gives a typical lock time value for the PLL.
5.2
Configuration examples
The STA538 PLL can be configured in two ways:
●
default startup configuration
●
direct PLL programming
The default startup configuration reads the device’s defaults. With this configuration, it is not
necessary to program the PLL dividers directly as some presets are used. In this mode, the
oversampling ratio between pins XTI (or MCLK33) and LRCLKI is fixed to 256.
The direct PLL programming bypasses the automatic presets allowing direct programming
of the PLL dividers.
The output PLL frequency can be determined as following:
Output division factor:
ODF = 2
Relation between input and output clock frequency:
FINFIN = FXTI / IDF
If register bit PLLCFG0.FRAC_CTRL = 1
FVCO = FINFIN * (LDF + FRACT/2
16 + 1/217)
FPHI = FVCO / ODF
When register bit PLLCFG0.DITHER_DISABLE[1] = 1, the 1/217 factor is not in the
multiplication. This is recommended in order to keep register bit
PLLCFG0.DITHER_DISABLE[1] = 0, otherwise there can be spurious signals in the output
clock spectrum.
C2
R1
C1
Vc
Ground



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com