M58BW016DB datasheet(29/69 Pages) STMICROELECTRONICS

29 / 69 page

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

Command interface

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4.4

Read Status Register command

The Read Status Register command is used to read the Status Register. One Bus Write

cycle is required to issue the Read Status Register command. Once the command is issued

subsequent Bus Read operations read the Status Register until another command is issued.

The Status Register information is present on the output data bus (DQ1-DQ7) when Chip

Enable E and Output Enable G are at VIL and Output Disable is at VIH.

An interactive update of the Status Register bits is possible by toggling Output Enable or

Output Disable. It is also possible during a program or erase operation, by deactivating the

device with Chip Enable at VIH and then reactivating it with Chip Enable and Output Enable

at VIL and Output Disable at VIH.

The content of the Status Register may also be read at the completion of a program, erase

or suspend operation. During a Block Erase or Program command, DQ7 indicates the

Program/Erase controller status. It is valid until the operation is completed or suspended.

See the section on the Status Register and Table 11 for details on the definitions of the

Status Register bits.

4.5

Clear Status Register command

The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status

Once the command is issued the memory returns to its previous mode, subsequent Bus

Read operations continue to output the same data.

The bits in the Status Register are sticky and do not automatically return to ‘0’ when a new

Program or Erase command is issued. If any error occurs then it is essential to clear any

error bits in the Status Register by issuing the Clear Status Register command before

attempting a new Program, Erase or Resume command.

M58BW016DB bảng dữ liệu(PDF) 29 Page - STMicroelectronics