M48Z35AV datasheet(11/24 Pages) STMICROELECTRONICS

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M48Z35AV

Operating modes

11/24

Table 4.

Write mode AC characteristics

2.3

Data retention mode

With valid VCC applied, the M48Z35AV operates as a conventional BYTEWIDE™ static

RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write

protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs

become high impedance, and all inputs are treated as “Don't care.”

Note:

A power failure during a WRITE cycle may corrupt data at the currently addressed location,

but does not jeopardize the rest of the RAM's content. At voltages below VPFD(min), the

user can be assured the memory will be in a write protected state, provided the VCC fall time

is not less than tF. The M48Z35AV may respond to transient noise spikes on VCC that reach

into the deselect window during the time the device is sampling VCC. Therefore, decoupling

of the power supply lines is recommended.

When VCC drops below VSO, the control circuit switches power to the internal battery which

preserves data. The internal button cell will maintain data in the M48Z35AV for an

accumulated period of at least 10 years (at 25°C) when VCC is less than VSO.

As system power returns and VCC rises above VSO, the battery is disconnected, and the

power supply is switched to external VCC. Write protection continues until VCC reaches

VPFD(min) plus tREC(min). Normal RAM operation can resume tREC after VCC exceeds

VPFD(max).

Symbol

Parameter(1)

Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 3.0 to 3.6V (except where noted).

M48Z35AV

Unit

–100

Min

Max

tAVAV

WRITE cycle time

100

tAVWL

Address valid to WRITE enable low

tAVEL

Address valid to chip enable low

tWLWH

WRITE enable pulse width

tELEH

Chip enable low to chip enable high

tWHAX

WRITE enable high to address transition

tEHAX

Chip enable high to address transition

tDVWH

Input valid to WRITE enable high

tDVEH

Input valid to chip enable high

tWHDX

WRITE enable high to input transition

tEHDX

Chip enable high to input transition

tWLQZ

(2)(3)

CL = 5pF (see Figure 10 on page 15).

If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

WRITE enable low to output Hi-Z

tAVWH

Address valid to WRITE enable high

tAVEH

Address valid to chip enable high

tWHQX

(2)(3)

WRITE enable high to output transition

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