TMP86CS49UG datasheet(202/252 Pages) TOSHIBA

202 / 252 page

Page 188

15. Synchronous Serial Interface (SIO2)

15.3 Function

TMP86CS49UG

Figure 15-11 Example of External Clock and MSB Receive Mode

(4) Receive error processing

Receive errors occur on the following situation. To protect SIO2RDB and the shift register con-

tents, the received data is ignored while the SIO2SR<RXERR> is “1”.

• Shift operation is finished before reading out received data from SIO2RDB at

SIO2SR<RXF> is “1” in an external clock operation.

If receive error occurs, set the SIO2CR<SIOS> to “0” for reading the data that received

immediately before error occurence. And read the data from SIO2RDB. Data in shift register

(at errors occur) can be read by reading the SIO2RDB again.

When SIO2SR<RXERR> is cleared to “0” after reading the received data, SIO2SR<RXF> is

cleared to “0”.

After clearing SIO2CR<SIOS> to “0”, when 8-bit serial clock is input to SCK2 pin, receive

operation is stopped. To restart the receive operation, confirm that SIO2SR<SIOF> is cleared

to “0”.

If the receive error occurs, set the SIO2CR<SIOINH> to “1” for stopping the receive opera-

tion immediately. In this case, SIO2CR<SIOS>, SIO2SR register, SIO2RDB register and

SIO2TDB register are initialized.

Writing transmit

data C

Writing transmit

data B

Writing transmit

data A

A7 A6

A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0

Start shift

operation

Start shift

operation

Start shift

operation

Clearing SIOS

Reading received data

SIO2CR<SIOS>

SIO2SR<SIOF>

SIO2SR<SEF>

SCK2

SI2 pin

SIO2SR<RXF>

INTSIO2

interrupt

request

SIO2RDB

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