TMP88CS34FG datasheet(92/215 Pages) TOSHIBA

92 / 215 page

TMP88CS34/CP34

2007-09-12

88CS34-92

(3) Serial clock

a. Clock source

The SCK (bits 2 to 0 in SBICRA) is used to select a maximum transfer frequency

output from the SCL pin in the master mode. Set a communication baud rate that

meets the I2C bus specification, such as the shortest pulse width of tLOW, based

on the equations shown below.

Four or more machine cycles are required for both high and low levels of pulse width

in the external clock which is input from SCL pin.

Note:

Since the I2C of TMP88CS34/CP34 can not be used as the Fast mode and the High

Speed mode, do not set SCK as the frequency that is over 100 kHz.

Figure 2.9.7 Clock Source

b. Clock synchronization

In the I2C bus mode, in order to drive a bus with a wired AND, a master device which

pulls down a clock pulse to low will, in the first place, invalidate a clock pulse of

another master device which generates a high-level clock pulse.

The serial bus interface circuit has a clock synchronization function. This function

ensures normal transfer even if there are two or more masters on the same bus.

The example explains clock synchronization procedures when two masters

simultaneously exist on a bus.

Figure 2.9.8 Clock Synchronization

As Master 1 pulls down the SCL pin to the low level at point “a”, the SCL line of the

bus becomes the low level. After detecting this situation, Master 2 resets counting a

clock pulse in the high level and sets the SCL pin to the low level.

Master 1 finishes counting a clock pulse in the low level at point “b” and sets the SCL

1/fscl

tLOW = 2

n/fc

tHIGH = 2

n/fc

+ 8/fc

fscl

= 1/(tLow + tHIGH)

Note: fc: High-frequency clock

SCK

(bits 2 to 0 in the SBICRA)

DV1CK

= 0

DV1CK

= 1

000

001

010

011

100

101

110

tHIGH

tLOW

tSCKL tSCKH

tSCKL , tSCKH > 4 tcyc

Note: tcyc

= 4/fc (in NORMAL mode, IDLE mode)

SCL pin (Master 1)

SCL pin (Master 2)

SCL (Bus)

wait

Count start

Count reset

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