UPSD3422EB40U6 datasheet(60/293 Pages) STMICROELECTRONICS

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MCU clock generation

uPSD34xx

60/293

14.2.2

USB_CLK

The uPSD34xx has a dedicated analog phase locked loop (PLL) that can be configured to

generate the 48MHz USB_CLK clock on a wide range of fOSC frequencies. The USB_CLK

must be at 48MHz for the USB to function properly.

The PLL is enabled after power up. The power on lock time for the PLL clock is about 200µs,

and the firmware should wait that much time before enabling the USB_CLK by setting the

UPLLCE Bit in the CCON0 Register to '1.' The PLL is disabled in Power-down mode, it can

also be disabled or enabled by writing to the PLLEN Bit in the CCON0 Register.

The PLL output clock frequency (fUSB_CLK) can be determined by using the following

formula:

where PLLM and PLLD are the multiplier and divisor that are specified in the CCON1

generate a stable USB_CLK:

–1

≤ PLLM ≤ 30 (binary: [11111] ≤ PLLM[4:0] ≤ [11110]),

–1

≤ PLLD ≤ 14 (binary: [1111] ≤ PLLD[3:0] ≤ [1110]), and

fOSC/(PLLD+2) must be equal to or greater than 3MHz.

The USB requires a 48MHz clock to operate correctly. The PLLM[4:0] and PLLD[3:0] values

must be selected so as to generate a USB_CLK that is as close to 48MHz as possible at

different oscillator frequencies (fOSC). Table 21 lists some of the PLLM and PLLD values that

can be used on common fOSC frequencies.

Table 21.

PLLM and PLLD Values for Different fOSC Frequencies

fOSC

(MHz)

PLLM[4:0]

PLLD[3:0]

fUSB_CLK

(MHz)

decimal

binary

decimal

binary

40.0

10110

1000

48.0

36.0

00110

0001

48.0

33.0

11110

1001

48.0

30.0

01110

0011

48.0

24.0

10010

0011

48.0

16.0

11100

0011

48.0

12.0

11110

0010

48.0

8.0

10110

0000

48.0

6.0

11110

0000

48.0

3.0

11110

–1

1111

48.0

USBCLK

OSC

PLLM

()

[]

PLLD

() 2

[]

⁄

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