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Axelite Confidential Materials, do not copy or distribute without written consent.

Rev.2.1 Oct.04, 2019

AX3050/A

Layout Guide

1

2

3

4

5

6

7

8

BS

LX

SENSE1

SENSE2

FB

COMP

IN

GND

C8

10uF

C1

100uF

C3

0.1uF

L1

68uH

C4

470uF

R1

50mΩ

C6

10uF

D1

SS34

R4

1kΩ

R3

4kΩ

C5

2.2nF

C7

optional

C2

2.2nF

R2

8.2kΩ

AX3050

GND

VIN

VOUT

GND

EP

Recommended layout guidelines are as follows:

1. Connect the 10µF VIN bypass capacitor next to the IN pin with a short return to the GND

pin.

2. Keep the BS to LX bypass capacitor near both pins as it provides the internal high-side

FET gate driver.

3. Keep the LX traces as short as is practically possible as these carry high peak currents to

decrease the EMI issue.

4. Carefully connect the noise sensitive signals such as FB, COMP, SENSE1 and SENSE2 as

close to the IC as practically possible.

5. SENSE1 and SENSE2 should be connected to R1 resistor directly to provide accurate

current sensing.

6. The Exposed Pad (EP) should be connected to any internal PCB ground planes using

multiple vias directly under the IC for best thermal performance.