The device intentionally interrupts the switching activities when two conditions happen together:

1. The peak inductor current required is lower than ISKIP

2. The voltage on the FB pin is higher than the reference voltage 0.85 V

A new switching cycle takes place once the voltage on the FB pins becomes lower than 0.85 V. The HS switch is

kept on until the inductor current reaches ISKIP. The amount of inductor peak current is independent of the

required conversion and component selection.

Once the current on the HS reaches the defined value, the device turns the HS off and turns the LS on. The LS is

kept enabled until one of the following conditions occurs:

1. The inductor current sensed by the LS becomes equal to zero

2. The switching period has expired

If, at the end of the switching cycle, the voltage on the FB (Feedback) pin is still above the reference voltage, the

LS (low-side switch) remains enabled until the inductor current becomes equal to zero. Otherwise, the device

turns on the HS again and starts a new switching pulse.

During the burst pulse, if the energy transferred to COUT increases the VFB level enough above the reference

voltage, the device interrupts the switching activities. The new cycle takes place only when VFB becomes lower

than the reference. Otherwise, as soon as the LS is turned off the HS is turned on.

Given the energy stored in the inductor during a burst, the voltage ripple depends on the capacitor value:

VOUT_RIPPLE=ΔQILCOUT=∫0TBURSTILt dt

COUT

(1)

In case of a very light-load condition in LCM, the device can enter into sleep mode with minimized input current

absorption.

6.3.2

Low noise mode (LNM)

Low noise mode implements a forced PWM operation over the different loading conditions. The LNM features a

constant switching frequency to minimize the noise in the final application and a constant voltage ripple at fixed

VIN.

The regulator in steady loading condition operates in continuous conduction mode (CCM) over the different

loading conditions.

The triangular shape current ripple (with zero average value) flowing into the output capacitor gives the output

voltage ripple, which depends on the capacitor value and the equivalent resistive component (ESR).

Consequently, the output capacitor must be selected in order to have a voltage ripple compliant with the

application requirements.

VOUT RIPPLE=ESR∙∆ILMAX+ ∆ILMAX

8∙COUT∙fSW

(2)

Usually, the resistive component of the ripple can be neglected if the selected output capacitor is a multilayer

ceramic capacitor (MLCC).

6.4

Dithering

The internal dithering circuit changes the switching frequency in a range of ± 5%.

ΔFSW=5%⋅FSM

(3)

The device updates the frequency every clock period by fixed steps:

•

Ramps up in 63 steps from minimum to maximum FSW

•

Ramps down in 63 steps from maximum to minimum FSW

The modulation shape is almost triangular with a frequency of:

FDitℎering=FSW/126

(4)

DCP3601

Functional description

DS14782 - Rev 1

page 8/26