TMPR3916 datasheet(164/225 Pages) TOSHIBA

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Chapter 9 Synchronous Serial I/O (TXSEI)

Preliminary

9-9

This counter is implemented as a down counter. It is reloaded each time a transfer is completed. When

another transfer is buffered, the new transfer value will be loaded to the shift buffer after the timer has

expired and the transmission will start.

The Inter Frame Space Timer can be disabled by setting this register to “0” and two consecutive transfers

will be sent using only the minimum amount of time required to load the buffers between consecutive frames

(seamless transfer). When the counter reload value in the IFS register is “0” the inter frame space will be one

system clock cycle (16.67 ns at 60 MHz system clock).

When the prescaler is not used, the inter frame space can be calculated using the following formula:

SYS

IFS

(range: 16.67 ns up to 17.07

µs at 60 MHz system clock)

When using the prescaler, the inter frame space can be calculated using the following formula:

SYS

IFS

(

(range: 533.33 ns up to 546.13

µs at 60 MHz system clock)

The IFS register can be written in configuration mode and in active mode. Writing to the IFS register

always clears the Inter Frame Space counter. Therefore, if the shift buffer contains a message, which is

waiting to be transferred, this message will be sent immediately, as soon as the IFS register is being written.

This will also be the case, if the old value is rewritten to the register. If this behavior is not intended, it is

possible to wait for SIDLE flag becoming “0”, before writing to the register.

The IFSD flag in the SESR register is asserted for the time the transfer is delayed by the IFS mechanism.

SEI Slave Select Space Register (SESS)

Bit

3130

262524

Name



Bit

2322

212019

181716

Name



Bit

1514

131211

Name



Bit

543

210

Name

SESS

Bit

Name

Function

Reset

Value

R/W

31:8



Unused

0x000000

7:0

SESS

Slave Select Space: Time between assertion of slave select signal

and transmission start

R/W

The contents of this register is the reload value of the Slave Select Timer. Write accesses to this register

are possible in configuration mode and in active mode. Writing to this register clears the slave select counter.

This register is used to configure the amount of time, which is inserted between activating the slave select

output signal in master mode and starting the transfer and between the transfer end and deactivating the slave

select output signal. The time is guaranteed by an internal 8-bit down counter. The counter runs on SEI

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