TMS320DM6435 datasheet(97/252 Pages) TI

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3.7.3

Pin Multiplexing Details

TMS320DM6435

Digital Media Processor

SPRS344B – NOVEMBER 2006 – REVISED NOVEMBER 2007

This section discusses how to program each Pin Mux Block to select the desired peripheral functions.

The following steps can be used to determine pin muxing suitable for the application:

1. Understand the major configuration choices available for the specific application.

Device Major Configuration Choices: Figure 3-11 shown in Section 3.7, Multiplexed Pin

Configurations, provides a high-level view of the device pin muxing and can be used to determine

the possible mix of peripheral options for a specific application.

EMIFA/VPSS Block Major Configuration Choices: The EMIFA/VPSS block features extensive pin

multiplexing to accommodate a variety of applications. In addition to Figure 3-11, Section 3.7.3.11,

EMIFA/VPSS Block Muxing, provides more details on the Major Configuration choices for this

block.

2. See Section 3.7.3.1, Multiplexed Pins on DM6435, for a summary of all the multiplexed pins on this

device and the pin mux group they belong to.

3. Refer to the individual pin mux sections (Section 3.7.3.3, Host Block Muxing to Section 3.7.3.11,

EMIFA/VPSS Block Muxing) for pin muxing details for a specific pin mux block.

For peripherals that span multiple pin mux blocks, the user must select the appropriate pins for that

peripheral in all relevant pin mux blocks. For more details, see Section 3.7.3.2, Peripherals

Spanning Multiple Pin Mux Blocks .

For details on PINMUX0 and PINMUX1 registers, see Section 3.7.2.

3.7.3.1 Multiplexed Pins on DM6435

Table 3-21 summarizes all of the multiplexed pins on DM6435, the pin mux group for each pin, and the

PINMUX register fields that control the pin. For pin mux details, see the specific pin mux group section

(Section 3.7.3.3, Host Block Muxing to Section 3.7.3.11, EMIFA/VPSS Block Muxing). For a description of

the PINMUX register fields, see Section 3.7.2.

Table 3-21. Multiplexed Pins on DM6435

SIGNAL

PINMUX DESCRIPTION

ZWT

ZDU

NAME

PINMUX GROUP

CONTROLLED BY PINMUX BIT FIELDS

NO.

PCLK/GP[54]

A14

A18

EMIFA/VPSS Sub-Block 0

CCDCSEL

VD/GP[53]

A13

A17

EMIFA/VPSS Sub-Block 0

HVDSEL

HD/GP[52]

A15

A19

EMIFA/VPSS Sub-Block 0

HVDSEL

CI7(CCD15)/EM_A[13]/GP[51]

B10

A12

EMIFA/VPSS Sub-Block 0

AEM, AEAW, CI76SEL

CI6(CCD14)/EM_A[14]/GP[50]

A10

A13

EMIFA/VPSS Sub-Block 0

AEM, AEAW, CI76SEL

CI5(CCD13)/EM_A[15]/GP[49]

B11

C13

EMIFA/VPSS Sub-Block 0

AEM, AEAW, CI54SEL

CI4(CCD12)/EM_A[16]/GP[48]

C11

B13

EMIFA/VPSS Sub-Block 0

AEM, AEAW, CI54SEL

CI3(CCD11)/EM_A[17]/GP[47]

A11

B14

EMIFA/VPSS Sub-Block 0

AEM, AEAW, CI32SEL

CI2(CCD10)/EM_A[18]/GP[46]

D11

A14

EMIFA/VPSS Sub-Block 0

AEM, AEAW, CI32SEL

CI1(CCD9)/EM_A[19]/GP[45]

B12

C14

EMIFA/VPSS Sub-Block 0

AEM, AEAW, CI10SEL

CI0(CCD8)/EM_A[20]/GP[44]

C12

C15

EMIFA/VPSS Sub-Block 0

AEM, AEAW, CI10SEL

YI7(CCD7)/GP[43]

A12

A15

EMIFA/VPSS Sub-Block 0

CCDCSEL

YI6(CCD6)/GP[42]

B13

B15

EMIFA/VPSS Sub-Block 0

CCDCSEL

YI5(CCD5)/GP[41]

C13

B16

EMIFA/VPSS Sub-Block 0

CCDCSEL

YI4(CCD4)/GP[40]

D14

C18

EMIFA/VPSS Sub-Block 0

CCDCSEL

YI3(CCD3)/GP[39]

B14

A16

EMIFA/VPSS Sub-Block 0

CCDCSEL

YI2(CCD2)/GP[38]

C14

B17

EMIFA/VPSS Sub-Block 0

CCDCSEL

YI1(CCD1)/GP[37]

B15

B18

EMIFA/VPSS Sub-Block 0

CCDCSEL

YI0(CCD0)/GP[36]

C15

B19

EMIFA/VPSS Sub-Block 0

CCDCSEL

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