SM9501B

SEIKO NPC CORPORATION —2

BLOCK DIAGRAM

PIN DESCRIPTION

Number

Name

1. I: input, O: output, Ipu: input with pull-up resistor, –: supply pin

2. A: analog signal, D: digital signal

Description

1

VDDA

−

A

AGC amplifier (+) supply input

2

IN1

I

A

Antenna input 1 (fixed input)

3

IN3

I

A

Antenna input 3 (via analog switch)

4

IN2

I

A

Antenna input 2 (analog switch bypass)

5

FCN

Ipu

D

Analog switch control input (active LOW)

6

XO

O

A

Output for crystal filter

7

VSSA

−

A

AGC amplifier (–) supply input

8

XI

I

A

Input from crystal filter

9

LF

O

A

Rectifier LPF capacitor connection

10

CB

O

A

Bottom hold detector capacitor connection

11

CP

O

A

Peak hold detector capacitor connection

12

HLDN

Ipu

D

AGC gain hold control (active LOW)

13

VSS

−

A

Substrate (–) supply input

14

OUT

O

D

Clock time code output (active LOW)

15

PON

Ipu

D

Standby state control input (active LOW)

16

VDD

−

A

(+) supply input

−

TN

Ipu

D

AGC amplifier gain control switch (active LOW, for test mode)

VDDA

VSS

VDD

CP

AGC Control

Peak/Bottom

Hold Det.

Decoder

CB

HLDN

PON

Bias

Rectifier

LPF

AGC Amp

XI

FCN

OUT

LF

XO VSSA

Post Amp

IN1

IN3

IN2