TMS320C6421 datasheet(85/223 Pages) TI

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HostBlock(27pins)

(A)

GPIO(27)

HOSTBK=000

VLYNQ

(10)

GPIO(17)

VLYNQ

(10)

EMAC(MII)

(15)

MDIO

(2)

HOSTBK=001

HOSTBK=010

HOSTBK=011

HOSTBK=100

HPI(26)

GPIO(1)

MDIO

(2)

GPIO(10)

UART0DataBlock(2pins)

GPIO(2)

UR0DBK=0

UART

Data(2)

UR0DBK=1

UART0FlowControlBlock(2pins)

GPIO(2)

UR0FCBK=00

UART0

FlowCtrl(2)

UR0FCBK=01

PWM0(1)

UR0FCBK=10

GPIO(1)

Timer1Block(2pins)

GPIO(2)

TIM1BK=00

Timer1

(2)

TIM1BK=01

Timer0Block(2pins)

(C)

GPIO(2)

TIM0BK=00

Timer0

(2)

TIM0BK=01

McBSP0

CLKS0(1)

TIM0BK=11

Timer0

TINPOL (1)

PWM1Block(1pin)

GPIO

(1)

PWM1BK=0

PWM1

(1)

PWM1BK=1

CLKOUTBlock(1pin)

GPIO

(1)

CKOBK=00

CLKOUT

(1)

CKOBK=01

PWM2

(1)

CKOBK=10

SerialPortSub-Block0(6pins)

(C)

GPIO(6)

SPBK0=00

McBSP0

(6)

SPBK0=01

McASP0Receive

and3Serializers(6)

SPBK0=10

SerialPortSub-Block1(6pins)

GPIO(6)

SPBK1=00

McASP0

Transmitand

1Serializer(6)

SPBK1=10

EMIFA Block(61pins)

(A)(B)

MajorConfig

Option A

GPIO

MajorConfig

OptionB

EMAC(RMII)

MajorConfig

OptionC

GPIO

EMIFA

(Async)

Pinout

Mode2

32MBper

AEM=000,

RMII=0

AEM=000,

RMII=1

AEM=010,

RMII=0

GPIO

MajorConfig

OptionD

GPIO

EMIFA

(Async)

Pinout

Mode2

32MBper

AEM=010,

RMII=1

EMAC(RMII)

MajorConfig

OptionE

GPIO

8bEMIFA

(NAND)

Pinout

Mode5

AEM=101,

RMII=0

MajorConfig

OptionF

GPIO

8bEMIFA

(NAND)

Pinout

Mode5

AEM=101,

RMII=1

EMAC(RMII)

EMAC(MII)

(15)

TMS320C6421

Fixed-Point Digital Signal Processor

SPRS346C – JANUARY 2007 – REVISED NOVEMBER 2007

Default settings for PINMUX0 and PINMUX1 registers are underlined.

EMIFA Block: This figure only shows the Major Config Options in the EMIFA Block based on the AEM and RMII

settings. Actual pin functions in the EMIFA Block are further determined by other PINMUX fields.

McBSP0 pins span multiple blocks (Serial Port Sub-Block0 and Timer0 Block). Serial Port Sub-Block0 contains most

of the pins needed for McBSP0 operation. Timer0 Block contains the optional external clock source input CLKS0.

Figure 3-10. Pin Mux Block Selection

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