74LVC3G34 datasheet(7/14 Pages) NXP

7 / 14 page

74LVC3G34_5

Product data sheet

Rev. 05 — 5 October 2007

7 of 14

NXP Semiconductors

74LVC3G34

Triple buffer

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

∑(CL × VCC2 × fo) = sum of outputs.

12. AC waveforms

Measurement points are given in Table 9.

Logic levels: VOL and VOH are typical output voltage

levels that occur with the output load.

Test data is given in Table 10. Deﬁnitions for test

circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe

capacitance.

RT = Termination resistance should be equal to the

output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching

times.

Fig 7.

The data input (nA) to output (nY) propagation

delays

Fig 8.

Load circuitry for switching times

mnb072

nA input

nY output

tPLH

tPHL

GND

VOH

VOL

VEXT

VCC

mna616

DUT

Table 9.

Measurement points

Supply voltage

Input

Output

VCC

1.65 V to 1.95 V

0.5

× V

0.5

× V

2.3 V to 2.7 V

0.5

× V

0.5

× V

2.7 V

1.5 V

3.0 V to 3.6 V

1.5 V

4.5 V to 5.5 V

0.5

× VCC

0.5

× V

Table 10.

Test data

Supply voltage

Input

Load

VEXT

VCC

tr =tf

tPLH, tPHL

1.65 V to 1.95 V

VCC

≤ 2.0 ns

30 pF

1 k

Ω

open

2.3 V to 2.7 V

VCC

≤ 2.0 ns

30 pF

500

Ω

open

2.7 V

≤ 2.5 ns

50 pF

500

Ω

open

3.0 V to 3.6 V

2.7 V

≤ 2.5 ns

50 pF

500

Ω

open

4.5 V to 5.5 V

VCC

≤ 2.5 ns

50 pF

500

Ω

open

74LVC3G34 bảng dữ liệu(PDF) 7 Page - NXP Semiconductors

74LVC3G34 bảng dữ liệu(HTML) 7 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14

bảng dữ liệu tải về

Link URL