74LVC1G79_7

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 07 — 29 August 2007

8 of 16

NXP Semiconductors

74LVC1G79

Single D-type flip-flop; positive-edge trigger

N = number of inputs switching;

12. Waveforms

Measurement points are given in Table 9.

Fig 7.

Clock (CP) to output (Q) propagation delay times

mna443

CP input

Q output

GND

D input

GND

Measurement points are given in Table 9.

Fig 8.

Clock (CP) to output (Q) propagation delay times, clock pulse width, D to set-up times, the CP to D hold

times and maximum clock pulse frequency

mna647

GND

GND

CP input

D input

Q output