PI7C8150B datasheet(49/108 Pages) PERICOM

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PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 49 of 108

APRIL 2006 – Revision 2.02

5. Posted write transactions must be given opportunities to pass delayed read and write

requests and completions. Otherwise, deadlocks may occur when some bridges which

support delayed transactions and other bridges which do not support delayed transactions

are being used in the same system. A fairness algorithm is used to arbitrate between the

posted write queue and the delayed transaction queue.

5.4

DATA SYNCHRONIZATION

Data synchronization refers to the relationship between interrupt signaling and data

delivery. The PCI Local Bus Specification, Revision 2.3, provides the following alternative

methods for synchronizing data and interrupts:

The device signaling the interrupt performs a read of the data just written (software).

The device driver performs a read operation to any register in the interrupting device

before accessing data written by the device (software).

System hardware guarantees that write buffers are flushed before interrupts are

forwarded.

PI7C8150B does not have a hardware mechanism to guarantee data synchronization for

posted write transactions. Therefore, all posted write transactions must be followed by a

read operation, either from the device to the location just written (or some other location

along the same path), or from the device driver to one of the device registers.

ERROR HANDLING

PI7C8150B checks, forwards, and generates parity on both the primary and secondary

interfaces. To maintain transparency, PI7C8150B always tries to forward the existing

parity condition on one bus to the other bus, along with address and data. PI7C8150B

always attempts to be transparent when reporting errors, but this is not always possible,

given the presence of posted data and delayed transactions.

To support error reporting on the PCI bus, PI7C8150B implements the following:

PERR_L and SERR_L signals on both the primary and secondary interfaces

Primary status and secondary status registers

The device-specific P_SERR_L event disable register

This chapter provides detailed information about how PI7C8150B handles errors.

It also describes error status reporting and error operation disabling.

6.1

ADDRESS PARITY ERRORS

PI7C8150B checks address parity for all transactions on both buses, for all address and all

bus commands. When PI7C8150B detects an address parity error on the primary interface,

the following events occur:

06-0044

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