PCA9541BSSLASH03 datasheet(18/43 Pages) NXP

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PCA9541_5

Product data sheet

Rev. 05 — 1 October 2007

18 of 43

NXP Semiconductors

PCA9541

2-to-1 I2C-bus master selector with interrupt logic and reset

• PCA9541/03: default ‘no channel’ (no STOP detect)

After power-up and/or insertion of the device in the main I2C-bus, no channel will be

connected to the downstream channel. The device is ready to receive a START

condition and its address by a master.

If either register writes to its Control Register, then the connection between the

upstream and the downstream channels is determined by the values on the Control

Registers.

Thereafter, VDD must be lowered below 0.2 V to reset the device.

8.6 External reset

A reset can be accomplished by holding the RESET pin LOW for a minimum of tWL. The

PCA9541 registers and I2C-bus state machine will be held in their default states until the

RESET input is once again HIGH. This input typically requires a pull-up resistor to VDD.

Default states are:

• I2C-bus upstream Channel 0 connected to the I2C-bus downstream channel for the

PCA9541/01

• no I2C-bus upstream channel connected to the I2C-bus downstream channel for the

PCA9541/02 with Channel 0 connected to the downstream I2C-bus channel after

detection of a STOP on the upstream channel

• no I2C-bus upstream channel connected to the I2C-bus downstream channel for the

PCA9541/03.

PCA9541BS/03 bảng dữ liệu(PDF) 18 Page - NXP Semiconductors