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DESCRIPTION/ORDERING INFORMATION

or Y = A + B in positive logic.

D, DGV, NS, OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1A

1B

1Y

2A

2B

2Y

GND

4B

4A

4Y

3B

3A

3Y

RGY PACKAGE

(TOP VIEW)

1

14

7

8

2

3

4

5

6

13

12

11

10

9

4B

4A

4Y

3B

3A

1B

1Y

2A

2B

2Y

A

B

Y

SN74ALVC08

QUADRUPLE 2-INPUT POSITIVE-AND GATE

SCES101I – JULY 1997 – REVISED OCTOBER 2004

•

Operates From 1.65 V to 3.6 V

•

•

±24-mA Output Drive at 3.3 V

•

Latch-Up Performance Exceeds 250 mA Per

JESD 17

•

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

This quadruple 2-input positive-AND gate is designed

The device performs the Boolean function Y = A · B

ORDERING INFORMATION

ORDERABLE PART NUMBER

TOP-SIDE MARKING

QFN - RGY

Tape and reel

SN74ALVC08RGYR

VA08

Tube

SN74ALVC08D

SOIC - D

ALVC08

Tape and reel

SN74ALVC08DR

-40

°C to 85°C

SOP - NS

Tape and reel

SN74ALVC08NSR

ALVC08

TSSOP - PW

Tape and reel

SN74ALVC08PWR

VA08

TVSOP - DGV

Tape and reel

SN74ALVC08DGVR

VA08

(1)

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

Y

A

B

H

H

H

L

X

L

X

L

L

LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 1997–2004, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.