PCAL9722 datasheet(46/63 Pages) NXP

46 / 63 page

NXP Semiconductors

PCAL9722

Ultra low-voltage translating 22-bit SPI I/O expander with Agile I/O features, interrupt output and

reset

13 Dynamic characteristics

Over recommended operating free air temperature range, unless otherwise specified. See Figure 29.

VDD(SPI) ≤ 1.65

VDD(SPI) ≤ 5.5

Symbol

Parameter

Conditions

Min

Max

Min

Max

Unit

fSCLK

maximum input clock frequency

MHz

tLOW

LOW period of the SCLK clock

250

100

tHIGH

HIGH period of the SCLK clock

250

100

tDS

SDIN to SCLK set-up time

tDH

SDIN to SCLK hold time

tCSS

CSn to SCLK rise set-up time

100

tCS_HI

minimum CSn de-asserted HIGH

time

200

tCSH

SCLK fall to CSn de-asserted hold

time

tDIS(SDOUT) SDOUT disable time

CL = 100 pF

150

tV(SDOUT)

SDOUT valid time

CL = 100 pF

200

Table 66. SPI bus interface timing requirements

SCLK

tLOW tHIGH

1 / fSCLK

tCSS

tDS tDH

D23

D22

D21

SDIN

tCSH tCS_HI

D23

SDOUT

aaa-015956

tV(SDOUT)

tDIS(SDOUT)

Figure 28. Definition of timing

Over recommended operating free air temperature range, unless otherwise specified. See Figure 31.

SPI bus

Symbol

Parameter

Conditions

Min

Max

Unit

tw(rst)

reset pulse width

150

trec(rst)

reset recovery time

500

trst

reset time

[1]

600

Table 67. Reset timing requirements

[1]

Minimum time for SDOUT to become HIGH.

PCAL9722

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 1 May 2023

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