IMX91CEC datasheet(6/100 Pages) NXP

6 / 100 page

Some modules shown in this block diagram are not offered on all derivatives. This block diagram may also show

less modules than available in some derivatives. See Table 2 for details.

NOTE

3 Special signal considerations

Table 3 lists special signal considerations for the i.MX 91 processors. The signal names are listed in alphabetical order.

The package contact assignments can be found in Package information and contact assignments. Signal descriptions are

provided in the

i.MX 91 Reference Manual (IMX91RM).

Table 3. Special signal considerations

Signal Name

Remarks

CLKIN1/CLKIN2

CLKIN1 and CLKIN2 are input pins without internal pull-up and pull-down. An external 10K

pull-down resistor is recommended if they are not used.

These signals are No Connect (NC) and should be unconnected in the application.

ONOFF

A brief connection to GND in the OFF mode causes the internal power management state machine

to change the state to ON. In the ON mode, a brief connection to GND generates an interrupt

(intended to be a software-controllable power-down). Approximately five seconds (or more) to GND

causes a forced OFF.

POR_B

POR_B has no internal pull-up/down resistor, and requires external pull-up resistor

to NVCC_BBSM_1P8.

It is recommended that POR_B is properly handled during power up/down. Please refer to the EVK

design for details.

RTC_XTALI/RTC_XTALO To hit the exact oscillation frequency, the board capacitors must be reduced to account for the board

and chip parasitics. The integrated oscillation amplifier is self-biasing, but relatively weak. Care

must be taken to limit the parasitic leakage from RTC_XTALI and RTC_XTALO to either the power

or the ground (> 100 MΩ). This de-biases the amplifier and reduces the start-up margin.

If you want to feed an external low-frequency clock into RTC_XTALI, the RTC_XTALO pin must

remain unconnected or driven by a complementary signal. The logic level of this forcing clock

must not exceed the NVCC_BBSM_1P8 level and the frequency shall be < 50 kHz under the

typical conditions.

XTALI_24M/XTALO_24M The system requires 24 MHz on XTALI/XTALO. The crystal cannot be eliminated by the external

24 MHz oscillator.

The logic level of this forcing clock must not exceed the VDD_ANA0_1P8 level.

If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter

requirements. See On-chip oscillators and relevant interface specifications chapters for details.

3.1 Unused input and output guidance

If a function of the i.MX 91 is not used, the I/Os and power rails of that function can be terminated to reduce overall board power.

Table 4 is recommended connectivities for digital I/Os. Table 5 is recommended connectivities for USB.

NXP Semiconductors

IMX91CEC

i.MX 91 Application Processors Data Sheet for Commercial Products

IMX91CEC

All information provided in this document is subject to legal disclaimers.

Preliminary Data Sheet

Rev. 2 — 12 November 2024

Preliminary - Subject to Change Without Notice

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