FXLS8971CF datasheet(54/100 Pages) NXP

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NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

Bit

Name

WAKE_IDLE[7:0]

Reset

Access

R/W

Table 61. WAKE_IDLE_LSB register (address 1Ah) bit allocation

15.3.7 WAKE_IDLE_MSB register (address 1Bh)

Flexible Power Mode WAKE idle time MSB. The contents of this register are only meaningful when

SENS_CONFIG2[WAKE_PM[1:0]] = 1xb.

Bit

Name

WAKE_IDLE[11:8]

Reset

Access

R/W

Table 62. WAKE_IDLE_MSB register (address 1Bh) bit allocation

15.3.8 SLEEP_IDLE_LSB register (address 1Ch)

Flexible Power Mode SLEEP idle time LSB. The contents of this register are only meaningful when

SENS_CONFIG2[SLEEP_PM[1:0]] = 1xb. This register, along with SLEEP_IDLE_MSB, sets the unsigned

12-bit SLEEP mode idle-time (off-time). The counter time period is 312.5 µs/LSB, providing a range of 312.5

µs to 1.28 seconds. The idle time + measurement time (set by the SLEEP mode decimation factor) forms the

measurement period (ODR–1).

Bit

Name

SLEEP_IDLE[7:0]

Reset

Access

R/W

Table 63. SLEEP_IDLE_LSB register (address 1Ch) bit allocation

15.3.9 SLEEP_IDLE_MSB register (address 1Dh)

Flexible Power Mode SLEEP idle time MSB (nibble). The contents of this register are useful only when

SENS_CONFIG2[SLEEP_PM[1:0]] = 1xb.

Bit

Name

SLEEP_IDLE_TIME[11:8]

Reset

Access

R/W

Table 64. SLEEP_IDLE_MSB register (address 1Dh) bit allocation

15.3.10 ASLP_COUNT_LSB, ASLP_COUNT_MSB registers (addresses 1Eh to 1Fh)

The

ASLP_COUNT value sets the minimum number of ODR periods needed to transition from WAKE to SLEEP

mode when no event activity is detected. See Section 15.3.4 for events that may be monitored for inactivity in

order to trigger the transition to SLEEP mode when the internal counter reaches the

ASLP_COUNT value.

FXLS8971CF

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.1 — 7 March 2024

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