STMPE2401 datasheet(14/55 Pages) STMICROELECTRONICS

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I2C Interface

STMPE2401

14/55

I2C Interface

The features that are supported by the I2C interface are as below:

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I2C Slave device

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SDAT and SCLK operates from 1.8V to 3.3V

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Compliant to Philip I2C specification version 2.1

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Supports Standard (up to 100kbps) and Fast (up to 400kbps) modes.

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7-bit device addressing mode

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General Call

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Start/Restart/Stop

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Address up to 4 STMPE2401 devices via I2C

The address is selected by the state of two pins. The state of the pins will be read upon

reset and then the pins can be configured for normal operation. The pins will have a pull-up

or down to set the address. The I2C interface module allows the connected host system to

access the registers in the STMPE2401.

6.1

Start condition

A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state.

A Start condition must precede any data/command transfer. The device continuously

monitors for a Start condition and will not respond to any transaction unless one is

encountered.

6.2

Stop condition

A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state.

A Stop condition terminates communication between the slave device and bus master. A

read command that is followed by NoAck can be followed by a Stop condition to force the

slave device into idle mode. When the slave device is in idle mode, it is ready to receive the

next I2C transaction. A Stop condition at the end of a write command stops the write

operation to registers.

6.3

Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter

releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls

the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave

the SDATA in high state if it would to not acknowledge the receipt of the data.

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