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STW81101ATR bảng dữ liệu(PDF) 17 Page - STMicroelectronics |
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STW81101ATR bảng dữ liệu(HTML) 17 Page - STMicroelectronics |
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17 / 48 page ![]() STW81101 General description 17/48 4 General description Figure 1: Block diagram shows the separate blocks that, when integrated, form an Integer-N PLL frequency synthesizer. The STW81101 consists of two internal low-noise VCOs with buffer blocks, a divider by 2, a divider by 4, a low-noise PFD (phase frequency detector), a precise charge pump, a 10-bit programmable reference divider, two programmable counters and a programmable dual- modulus prescaler. The 5-bit A-counter and 12-bit B-counter, in conjunction with the dual modulus prescaler P/P+1 (16/17 or 19/20), implement an N integer divider, where N = B*P +A. The division ratio of both reference and VCO dividers is controlled through the selected digital interface (I2C bus or SPI). The selection of the digital interface type is done by the proper hardware connection of the pin DBUS_SEL (0 V for I2C bus, 3.3 V for SPI). All devices operate with a power supply of 3.3 V and can be powered down when not in use. |
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