PC912XDP512F0CAL datasheet(98/1350 Pages) FREESCALE

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Chapter 2 Clocks and Reset Generator (S12CRGV6)

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

2.4

Functional Description

2.4.1

Functional Blocks

2.4.1.1

Phase Locked Loop (PLL)

The PLL is used to run the MCU from a different time base than the incoming OSCCLK. For increased

ﬂexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency. This offers

a ﬁner multiplication granularity. The PLL can multiply this reference clock by a multiple of 2, 4, 6,...

126,128 based on the SYNR register.

CAUTION

Although it is possible to set the two dividers to command a very high clock

frequency, do not exceed the speciﬁed bus frequency limit for the MCU.

If (PLLSEL = 1), Bus Clock = PLLCLK / 2

The PLL is a frequency generator that operates in either acquisition mode or tracking mode, depending on

the difference between the output frequency and the target frequency. The PLL can change between

acquisition and tracking modes either automatically or manually.

The VCO has a minimum operating frequency, which corresponds to the self clock mode frequency fSCM.

Figure 2-16. PLL Functional Diagram

PLLCLK

OSCCLK

SYNR

[]

REFDV

[]

------------------------------------

REDUCED

CONSUMPTION

OSCILLATOR

EXTAL

XTAL

OSCCLK

PLLCLK

REFERENCE

PROGRAMMABLE

DIVIDER

PDET

PHASE

DETECTOR

REFDV <5:0>

LOOP

PROGRAMMABLE

DIVIDER

SYN <5:0>

CPUMP

VCO

LOCK

LOOP

FILTER

XFC

DOWN

LOCK

DETECTOR

REFERENCE

FEEDBACK

VDDPLL

VDDPLL/VSSPLL

CRYSTAL

MONITOR

VDDPLL/VSSPLL

VDD/VSS

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