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Rev 1.0

16/07/2021

CMOS High Voltage Logic – CD40106B

DC Electrical Characteristics T

A = -55 to +125°C unless otherwise stated

GUARANTEED LIMITS

PARAMETER

SYMBOL

VDD

CONDITIONS

25°C

85°C

FULL RANGE

3

UNITS

5V

VOUT = 0.5V

4.3

4.3

4.3

10V

VOUT = 1V

8.6

8.6

8.6

Maximum Positive -

Going Threshold

Voltage

VT+ MAX

15V

VOUT = 1.5V

12.9

12.9

12.9

V

5V

1.0

1.0

1.0

10V

2.0

2.0

2.0

Minimum

Hysteresis Voltage

(VT+ - VT-)

VH MIN

15V

3.0

3.0

3.0

V

5V

3.6

3.6

3.6

10V

7.2

7.2

7.2

Maximum

Hysteresis Voltage

(VT+ - VT-)

VH MAX

15V

10.8

10.8

10.8

V

5V

VOUT = 0.4V

0.52

0.44

0.36

10V

VOUT = 0.5V

1.30

1.10

0.90

LOW Level

Output Current

4

IOL

15V

VOUT = 1.5V

3.60

3.00

2.4

mA

5V

VOUT = 4.6V

-0.52

-0.44

-0.36

10V

VOUT = 9.5V

-1.30

-1.10

-0.90

HIGH Level

Output Current

4

IOH

15V

VOUT = 13.5V

-3.60

-3.00

-2.4

mA

15V

VIN = 0V

-0.30

-0.30

-1. 0

Input Current

IIN

15V

VIN = 15V

0.30

0.30

1.0

µA

5. Not production tested in die form, characterized by chip design.

6. Used to determine the no-load dynamic power consumption: PD = CPD VCC

2f + ICC VCC.

4. IOH and IOL are tested one output at a time.

AC Electrical Characteristics5 T

A = 25°C, CL = 50pF, RL = 200kΩ unless otherwise stated

PARAMETER

SYMBOL

VDD

CONDITIONS

TYPICAL

MAX

UNITS

5V

220

400

10V

80

200

Maximum

Propagation Delay,

Input to Output

(Figure 3)

tPLH, tPHL

15V

tr = tf = 20ns

70

160

ns

5V

100

200

10V

50

100

Maximum Output

Rise and Fall Time

(Figure 3)

tTLH, tTHL

15V

tr = tf = 20ns

40

80

ns

Input Capacitance

CIN

-

Any Input

5

7.5

pF

TYPICAL

Power Dissipation

Capacitance

Per Gate

6

CPD

-

-

14

pF