RT9702PB datasheet(14/16 Pages) RICHTEK

14 / 16 page

RT9702/A

DS9702/A-11

June 2007

www.richtek.com

ESD

Because USB is a hot insertion and removal system, USB

components (especially the connector pins) are subject

to electrostatic discharge (ESD) and should be qualified

to IEC801.2. The RT9702/A is designed to withstand a

8kV human body mode, as defined in MIL-STD-883C. The

requirements in IEC801.2 are much more stringent and

require additional capacitors for the RT9702/A to withstand

the higher ESD energy.

Low-ESR 1

μF ceramic bypass capacitors and output

capacitors should be placed as closely as possible to the

VIN and VOUT pins to increase the ESD immunity. The

RT9702/A may pass the requirements of IEC 1000-4-2

(EN 50082-1) level-4 for 15kV air discharge and 8kV contact

discharge tests when these capacitors are added.

PCB Layout

In order to meet the voltage drop, droop, and EMI

requirements, careful PCB layout is necessary. The

following guidelines must be considered:

Keep all VBUS traces as short as possible and use at

least 50-mil, 2 ounce copper for all VBUS traces.

Avoid vias as much as possible. If vias are necessary,

make them as large as feasible.

Place a ground plane under all circuitry to lower both

resistance and inductance and improve DC and transient

performance (Use a separate ground and power plans if

possible).

Place cuts in the ground plane between ports to help

reduce the coupling of transients between ports.

Locate the output capacitor and ferrite beads as close

to the USB connectors as possible to lower impedance

(mainly inductance) between the port and the capacitor

and improve transient load performance.

Locate the RT9702/A as close as possible to the output

port to limit switching noise.

Locate the ceramic bypass capacitors as close as

possible to the VIN pins of the RT9702/A.

GND

FLG

GND_BUS

USB

Controller

Board Layout

OUT

BUS

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