RT8012APQW datasheet(13/14 Pages) RICHTEK

13 / 14 page

RT8012A

DS8012A-01 March 2007

www.richtek.com

Preliminary

through inductor L is “chopped” between the main switch

and the synchronous switch. Thus, the series resistance

looking into the LX pin is a function of both top and bottom

MOSFET RDS(ON) and the duty cycle (DC) as follows :

RSW = RDS(ON)TOP x DC + RDS(ON)BOT x (1

−DC)

The RDS(ON) for both the top and bottom MOSFETs can be

obtained from the Typical Performance Characteristics

curves. Thus, to obtain I2R losses, simply add RSW to RL

and multiply the result by the square of the average output

current.

Other losses including CIN and COUT ESR dissipative

losses and inductor core losses generally account for less

than 2% of the total loss.

Checking Transient Response

The regulator loop response can be checked by looking

at the load transient response. Switching regulators take

several cycles to respond to a step in load current. When

a load step occurs, VOUT immediately shifts by an amount

equal to

ΔILOAD (ESR), where ESR is the effective series

resistance of COUT.

ΔILOAD also begins to charge or

discharge COUT generating a feedback error signal used

by the regulator to return VOUT to its steady-state value.

During this recovery time, VOUT can be monitored for

overshoot or ringing that would indicate a stability problem.

Thermal Considerations

For continuous operation, do not exceed the maximum

operation junction temperature 125

°C. The maximum

power dissipation depends on the thermal resistance of

IC package, PCB layout, the rate of surroundings airflow

and temperature differential between junction to ambient.

The maximum power dissipation can be calculated by

following formula :

PD(MAX) = ( TJ(MAX) - TA ) /

θJA

Where TJ(MAX) is the maximum operation junction

temperature 125

°C, TAis the ambient temperature and the

θJA is the junction to ambient thermal resistance.

For recommended operating conditions specification of

RT8012A, where TJ(MAX) is the maximum junction

temperature of the die (125

°C) and TA is the maximum

ambient temperature. The junction to ambient thermal

resistance

θJA is layout dependent. For WQFN-16L 4x4

packages, the thermal resistance

θJA is 54°C/W on the

standard JEDEC 51-7 four-layers thermal test board. The

maximum power dissipation at TA= 25

°C can be calculated

by following formula :

PD(MAX) = ( 125

°C − 25°C) / 54°C/W = 1.852W for

WQFN-16L 4x4 packages

The maximum power dissipation depends on operating

ambient temperature for fixed TJ(MAX) and thermal

resistance

θJA. For RT8012A packages, the Figure 4 of

derating curves allows the designer to see the effect of

rising ambient temperature on the maximum power

allowed.

Figure 4. Derating Curves for RT8012A Packages

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

100

125

Temperature (°C)

WQFN 16L 4x4

Four Layers PCB

Layout Considerations

Follow the PCB layout guidelines for optimal performance

of RT8012A.

Keep the traces of the main current paths as short and

wide as possible.

Put the input capacitor as close as possible to the device

pins (VIN and GND).

LX node is with high frequency voltage swing and should

be kept small area. Keep analog components away from

LX node to prevent stray capacitive noise pick-up.

Connect feedback network behind the output capacitors.

Keep the loop area small. Place the feedback

components near the RT8012A.

Connect all analog grounds to a command node and

then connect the command node to the power ground

behind the output capacitors.

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