AMMLP series

Low Power, Low Jitter MEMS Oscillator

Revision:

Initial Release 4/30/2024

Page 4

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Pin #

Pin Name

Description

1

OE

Output Enable: Note 6&8

Logic High or No Connect: Output Enabled

Logic Low: Output Disabled (High impedance)

External pull-up recommended for normal operation.

STBY

Standby: Note 6&8

Logic High or No Connect: Output Enabled

Logic Low: Output Disabled - Device is in Standby (Both output buffer and PLL disabled)

External pull-up recommended for normal operation.

2

GND

Ground

3

Output

Oscillator clock output

4

VDD

Power Supply: 1.71V to 3.63V Note 7

Pin Functions

Note 6:

If pin 1 is high or floating, there will be frequency output. If pin 1 is low, output will be disabled.

Note 7:

Bypass with 0.1 μF capacitor placed as close to VDD pin as possible.

Note 8:

70 KΩ (minimum) internal pull-up resistor present on pin 1.

Output Waveform