This Data Sheet may be revised by subsequent versions

©2004 Eon Silicon Solution, Inc., www.essi.com.tw

or modifications due to changes in technical specifications.

11

EN25B32

Rev. C, Issue Date: 2007/06/21

Table 3a. Protected Area Sizes- Bottom Boot Sector Organization

Status Register

Content

Memory Content

BP2

Bit

BP1

Bit

BP0

Bit

Protect Sectors

Addresses

Density(KB)

Portion

1

1

1

All

000000h-3FFFFFh

4096KB

All

1

1

0

Sector 0 to 35

000000h-1FFFFFh

2048KB

Lower 1/2

1

0

1

Sector 0 to 4

000000h-00FFFFh

64KB

Lower 1/64

1

0

0

Sector 0 to 3

000000h-007FFFh

32KB

Lower 1/128

0

1

1

Sector 0 to 2

000000h-003FFFh

16KB

Lower 1/256

0

1

0

Sector 0 to 1

000000h-001FFFh

8KB

Lower 1/512

0

0

1

Sector 0

000000h-000FFFh

4KB

Lower 1/1024

0

0

0

None

None

None

None

Table 3b. Protected Area Sizes- Top Boot Sector Organization

Status Register

Content

Memory Content

BP2

Bit

BP1

Bit

BP0

Bit

Protect Sectors

Addresses

Density(KB)

Portion

0

0

0

None

None

None

None

0

0

1

Sector 67

3FF000h-3FFFFFh

4KB

Upper 1/1024

0

1

0

Sector 66 to 67

3FE000h-3FFFFFh

8KB

Upper 1/512

0

1

1

Sector 65 to 67

3FC000h-3FFFFFh

16KB

Upper 1/256

1

0

0

Sector 64 to 67

3F8000h-3FFFFFh

32KB

Upper 1/128

1

0

1

Sector 63 to 67

3F0000h-3FFFFFh

64KB

Upper 1/64

1

1

0

Sector 32 to 67

200000h-3FFFFFh

2048KB

Upper 1/2

1

1

1

All

000000h-3FFFFFh

4096KB

All

Hold Function

The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the

clocking sequence. However, taking this signal Low does not terminate any Write Status Register,

Program or Erase cycle that is currently in progress.

To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold condition

starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (CLK)

being Low (as shown in Figure 4.).

The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with

Serial Clock (CLK) being Low.

If the falling edge does not coincide with Serial Clock (CLK) being Low, the Hold condition starts after

Serial Clock (CLK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (CLK)

being Low, the Hold condition ends after Serial Clock (CLK) next goes Low. (This is shown in Figure 4.).

During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and

Serial Clock (CLK) are Don’t Care.

Normally, the device is kept selected, with Chip Select (CS#) driven Low, for the whole duration of the

Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment

of entering the Hold condition.

If Chip Select (CS#) goes High while the device is in the Hold condition, this has the effect of resetting the

internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD)

High, and then to drive Chip Select (CS#) Low. This prevents the device from going back to the Hold

condition.