Internet Data Sheet

Rev. 1.0, 2006-12

17

11032006-VX0M-M6IH

HYS72T512341H[H/J/K]P-[3.7/5]-B

Registered DDR2 SDRAM Modules

TABLE 14

Definitions for

I

DD

Distributed Refresh Current

t

commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.

I

DD5D

Self-Refresh Current

CKE

≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data

bus inputs are FLOATING.

I

I

DD6

All Bank Interleave Read Current

All banks are being interleaved at minimum

t

and address bus inputs are STABLE during DESELECTS.

I

I

DD7

6)

1)

V

2)

I

3) Definitions for

I

4) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode

I

DD2P

5) For details and notes see the relevant Qimonda component data sheet

6)

I

buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.

Parameter

Description

LOW

V

STABLE

Inputs are stable at a HIGH or LOW level

FLOATING

Inputs are

V

SWITCHING

Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control

signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ

signals not including mask or strobes

Parameter

Symbol Note

1)2)3)4)5)