ML145151 datasheet(21/35 Pages) LANSDALE

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Issue A

ML145158

LANSDALE Semiconductor, Inc.

PIN DESCRIPTIONS

INPUT PINS

fin Frequency Input (Pin 8)

Input frequency from VCO output. A rising edge signal on

this input decrements the ÷ A and ÷ N counters. This input has

an inverter biased in the linear region to allow use with AC

coupled signals as low as 500 mV p–p. For larger amplitude

signals (standard CMOS logic levels), DC coupling may be

used.

CLK, DATA

Shift Clock, Serial Data Inputs (Pins 9, 10)

Each low–to–high transition of the CLK shifts one bit of

data into the on–chip shift registers. The last data bit entered

determines which counter storage latch is activated; a logic 1

selects the reference counter latch and a logic 0 selects the

÷ A, ÷ N counter latch. The data entry format is as follows:

ENB

Latch Enable Input (Pin 11)

A logic high on this pin latches the data from the shift regis-

ter into the reference divider or ÷ N, ÷ A latches depending on

the control bit. The reference divider latches are activated if the

control bit is at a logic high and the ÷ N, ÷ A latches are acti-

vated if the control bit is at a logic low. A logic low on this pin

allows the user to change the data in the shift registers without

affecting the counters. ENB is normally low and is pulsed high

to transfer data to the latches.

OSCin, OSCout

Reference Oscillator Input/Output (Pins 1, 2)

These pins form an on–chip reference oscillator when con-

nected to terminals of an external parallel resonant crystal.

Frequency setting capacitors of appropriate value must be con-

nected from OSCin to ground and OSCout to ground. OSCin

may also serve as the input for an externally–generated refer-

ence signal. This signal is typically AC coupled to OSCin, but

for larger amplitude signals (standard CMOS logic levels) DC

coupling may also be used. In the external reference mode, no

connection is required to OSCout.

FIRST DATA BIT INTO SHIFT REGISTER

÷ R

÷ N

FIRST DATA BIT INTO SHIFT REGISTER

÷ A

14–BIT SHIFT REGISTER

7–BIT

÷ A

COUNTER

φV

ML145158 BLOCK DIAGRAM

φR

REFERENCE COUNTER LATCH

PHASE

DETECTOR

PHASE

DETECTOR

LOCK

DETECT

PDout

fin

OSCin

OSCout

ENB

7–BIT S/R

DATA

CLK

REFout

÷ A COUNTER

LATCH

14–BIT

÷ RCOUNTER

1–BIT

CONTROL

S/R

10–BIT S/R

÷ N COUNTER

LATCH

10–BIT

÷ N

COUNTER

CONTROL LOGIC

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