GL9701 datasheet(49/75 Pages) GENESYS

49 / 75 page

GL9701 PCI Express

TM to PCI Bridge

Page 49

6.29 Offset 74h: PCI Express Device Capabilities Register

Bits

Type

Default

Description

2:0

010b

Max_Payload_Size Supported –512 bytes max payload size is

supported.

4:3

00b

Phantom Functions Supported –No function number bits used

for Phantom Functions; device may implement all function

numbers.

Extended Tag Field Supported –5-bit Tag field supported

8:6

111b

Endpoint L0s Acceptable Latency –The acceptable total latency

that an Endpoint can withstand due to the transition from L0s state

to the L0 state is more than 4 µs.

11:9

111b

Endpoint L1 Acceptable Latency –The acceptable latency that an

Endpoint can withstand due to the transition from L1 state to the

L0 state is more than 64 µs.

Attention Button Present – Not supported.

Attention Indicator Present – Not supported.

Power Indicator Present – Not supported.

17:15

RsvdP

000b

RsvdP

25:18

00h

Captured Slot Power Limit Value – In combination with the Slot

Power Limit Scale value, specifies the upper limit on power

supplied by slot. This value is set by the Set_Slot_Power_Limit

Message

27:26

00b

Captured Slot Power Limit Scale – Specifies the scale used for

the Slot Power Limit Value. This value is set by the

Set_Slot_Power_Limit Message.

6.30 Offset 78h: PCI Express Device Control Register

Bits

Type

Default

Description

Correctable Error Reporting Enable – This bit controls

reporting of correctable errors.

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