LANSDALE Semiconductor, Inc.

ML688T

www.lansdale.com

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Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili-

ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit

described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which

may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may

vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s

technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.

OPERATING NOTES

1. If any of the input of ML688 is not used, it should be

returned through a 2k

Ω resistor to VCC. This is par-

ticularly true of the SET and RESET inputs, as these

are most susceptible to noise. A single resistor may

be used for up to 300 unused inputs.

2. The truth table shown for ML688 is completely valid only

when the J & K inputs remain unchanged throughout the

entire period when the clock input is high. This is a master-

slave device, with the master receiving its instructions

while the clock input is high. A study of the logic diagram

will reveal that the J & K inputs are such that the flip-flop

should reverse states at the negative clock transition, it will

reverse state on the negative clock transition regardless of

any subsequent change of J or K.

The master-slave principle as used in this device leads

to the aforementioned restriction which may not be desir

able in some instances. However, it can be shown that an

MHTL system is inherently more susceptible to negative-

going nose than positive-going due to the difference in

impedance levels.The design of the ML688 is such that

negative-going noise appearing on the J or K inputs must

last throughout the entire duration of the clock pulse to

have any effect. The net result can well be a system with

greater than expected noise immunity if care is used in

other areas of the system.

3. The SET and RESET inputs control the output states when

activated while the clock is low. A logic zero on these

inputs has no immediate effect on the outputs if the clock

input is high, but it can change the state of the master sec-

tion. As an example, consider SET & RESET high, all

other inputs and Q output low. If a clock pulse is received

under these conditions, the output will not change.

However, if SET is momentarily activated with a logic zero

while clock is high, the flip-flop will reverse states on the

trailing edge of the clock. This provides a means of syn

chronous data entry into the devices without using J & K

inputs. This feature is quite useful in certain types of shift

registers and counters made with the ML688.

4. As with other saturated logic devices, input rise and fall

times should be minimized for best operation. The most

critical input in this respect is CLOCK, which should have

a transition time of less than 0.5

µ sec in either direction

(measured from 6.5 to 8.5 volts). Failure to observe this

restriction may result in triggering on positive clock transi-

tion or multiple triggering on negative clock transition.